The statements in this section merely provide background information related to the present disclosure and do not necessarily constitute prior art.
Generally, a semiconductor device receives an external clock signal, generates an internal clock signal, and uses the internal clock signal as a reference for adjusting the operation timing of the internal circuit. In order to generate the internal clock signal, the semiconductor device includes an internal clock signal generation circuit. Typical examples of the internal clock signal generation circuit include a phase locked loop (PLL) and a delay locked loop (DLL).
The internal clock signal generation circuit receives a clock signal serving as a reference (hereinafter referred to as a reference clock signal) and generates an internal clock signal having a phase corresponding thereto. The internal clock signal generation circuit performs a locking operation since most internal clock signals that are initially generated do not have a phase corresponding to the reference clock signal. Here, the locking operation means an operation of adjusting the phase of the internal clock signal to the phase corresponding to the reference clock signal.
In order to perform the locking operation, the internal clock signal generation circuit is required to perform a phase detection operation for detecting a phase difference between the internal clock signal and the reference clock signal. And, the internal clock signal generation circuit is required to perform a phase calibration operation for calibrating the phase of the internal clock signal depending on the result of the detection.
The internal clock signal generation circuit is required to include a phase detection circuit and an phase adjustment circuit for performing the locking operation.